SRAM yield is limited by intrinsic (mismatch, targeting, etc.) and extrinsic (defect) mechanisms. To achieve a desired yield percentage with respect to a SRAM array, it is important to maintain defect Pareto to quantify extrinsic yield impact and address top extrinsic yield limiters. Both intrinsic and extrinsic defects may be found during the SRAM development phase; however, because only the intrinsic defects can be optimized, it is important to identify the extrinsic defects, e.g., a short, as early as possible to determine what part of the process is causing the defect.
Traditionally, extrinsic defects could be identified at high voltage, e.g., Vmax or higher, and then the corresponding bit could be submitted for further failure analysis (FA) to define the high voltage defect Pareto that needs to be addressed to improve yield. In contrast, only intrinsic mechanisms could be detected at low voltage, e.g., less than Vmax or from Vnom to Vmin. However, in the advanced technology nodes, a new category of fails is observed, known as the Low Voltage Extrinsics. This is a class of defects that can only be detected at voltages lower than Vmax, but disappear at high Vdds. As a result, these defects cannot be detected using a simple Vmax based test and FA. Since these defect mechanisms limit the low voltage yield, it is critical to identify and improve them early in the development phase since they cannot be addressed by intrinsic improvement alone. With large numbers of bits failing at low VDD within a region of an array and generally limited FA resources, it is difficult to efficiently select the right defect driven failing bits for FA. Normally, a few bits that failed at higher voltages than Vmin are randomly selected for FA analysis. However, just because the bit failed at higher voltages does not mean that the failure was extrinsic in nature. Moreover, a large number of such submissions result in No Defect Found (NDF), since the bits submitted for FA are intrinsic and not defect driven. This, in turn, limits the ability to efficiently characterize low voltage defects.
A need therefore exists for a methodology and apparatus enabling a simple identification of non-intrinsic defect bits from a population of low voltage failing bits for FA to characterize the extrinsic failure mechanisms.